How? Since the cathode resistor sees a fixed voltage at its cathode end, the perturbation at the amplifier's output provokes an increase or decrease of current flowing through the cathode resistor. Thus, any perturbation at the output is relayed to the phase splitter's plate resistor. The first is marked by the cathode side connection, where the output directly (or, somewhat indirectly, via a coupling capacitor or a zener or a voltage regulator) couples to the other side of the phase splitter's cathode resistor.
The operation is the same as the 2-input TTL NAND gate.The Tube CAD Journal, Totem-Pole Output Stage It is the same as that we discussed in the 2-input TTL NAND gate circuit, except that here, the input transistor Q 1 has three emitters instead of two. The following figure shows the circuit of the standard 3-input TTL NAND gate. Circuit of standard 3-input TTL NAND Gate With Q 2 turned ON, transistor Q 4 will also be turned ON.īoth the transistors at the output side will conduct and so the output at terminal will have LOW value, which is considered as logic 0. The diode D C at the collector-base junction is forward biased. When both the inputs A and B are high, both the diodes at the emitter-base junction will be reverse biased. The same operation will take place as explained above. When any one input, either A or B is low, the diode with low input will be forward biased. Since Q 3 is an emitter follower, the output at the terminal will also be HIGH, which is at logic 1.
With Q 2 open, the transistor Q 4 will also cut off. The supply voltage gets dropped in the resistor R 1 and it will not be sufficient to turn ON the transistor Q 2. So the current due to the supply voltage +V CC = 5 V will go to the ground through R 1 and the two diodes D A and D B. When both inputs A and B are low, both the diodes are forward biased. Diode D C represents the collector-base junction of transistor Q 2. In the figure, diodes, D A and D B represent the 2-input emitter junction of transistor Q 1.
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